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M54HC191 RAD-HARD 4 BIT SYNCHRONOUS UP/DOWN COUNTERS s s s s s s s s s s s HIGH SPEED: fMAX = 61 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 191 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9204-066 DILC-16 FPC-16 ORDER CODES PACKAGE DILC FPC FM M54HC191D M54HC191K EM M54HC191D1 M54HC191K1 DESCRIPTION The M54HC191 is an high speed CMOS 4-BIT SYNCHRONOUS UP/DOWN COUNTER fabricated with silicon gate C2MOS technology. State changes of the counter are synchronous with the LOW-to-HIGH transition of the Clock Pulse Input. PIN CONNECTION An asynchronous parallel load input overrides counting and loads the data present on the DATA inputs into the flip-flops, which makes it possible to use the circuits as programmable counters. A count enable input serves as the carry/borrow input in multi-stage counters. Control input, Down/ Up, determines whether a circuit counts up or down. A MAX/MIN output and a Ripple Clock output provide overflow/underflow indication and make possible a variety of methods for generating carry/borrow signals in multi-stage counter applications. All inputs are equipped with protection circuits against static discharge and transient excess voltage. March 2004 1/13 M54HC191 IEC LOGIC SYMBOLS INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN N 3, 2, 6, 7 4 5 11 12 13 14 15, 1, 10, 9 8 16 SYMBOL QA to QD NAME AND FUNCTION Flip-Flop Outputs Count Enable Input ENABLE (Active LOW) D/U Parallel Data Input LOAD Load Input (Active LOW) MA/MI OUT Terminal Count Output Ripple Clock Output RCO (Active LOW) Clock Input (LOW to CLOCK HIGH, edge triggered) DA to DD Data Inputs GND Ground (0V) VCC Positive Supply Voltage TRUTH TABLE INPUTS LOAD L H H H H ENABLE X L L H X D/U X L H X X CLOCK X QA a OUTPUTS FUNCTION QB b QC c QD d PRESET DATA UP COUNT DOWN COUNT NO COUNT NO COUNT UP COUNT DOWN COUNT NO CHANGE NO CHANGE X : Don't Care a - d: The level of steady state inputs a through d respectively 2/13 M54HC191 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 3/13 M54HC191 TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 50 300 -65 to +150 265 Unit V V V mA mA mA mA mW C C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 4/13 M54HC191 RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 80 A A V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH 5/13 M54HC191 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25C Min. Typ. 30 8 7 92 23 20 39 13 11 120 30 26 108 27 23 84 21 18 39 13 11 63 21 18 64 18 15 9 37 44 40 10 9 36 9 8 80 20 17 16 4 3 Max. 75 15 13 180 36 31 120 24 20 240 48 41 205 41 35 175 35 30 105 21 18 180 36 31 160 32 27 4 20 24 100 20 17 75 15 13 175 35 30 50 10 9 0 0 0 125 25 21 95 19 16 220 44 37 60 12 11 0 0 0 Value -40 to 85C Min. Max. 95 19 16 225 45 38 150 30 26 300 60 51 255 51 43 220 44 37 130 26 22 225 45 38 200 40 34 3.4 17 20 150 30 26 110 22 19 265 53 45 75 15 13 0 0 0 -55 to 125C Min. Max. 110 22 19 270 54 46 180 36 31 360 72 61 310 61 53 265 53 45 160 32 27 270 54 46 240 48 41 ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - Q) tPLH tPHL Propagation Delay Time (CLOCK - RCO) tPLH tPHL Propagation Delay Time (CLOCK MAX/MIN) tPLH tPHL Propagation Delay Time (LOAD - Q) tPLH tPHL Propagation Delay Time (DATA - Q) tPLH tPHL Propagation Delay Time (ENABLE RCO) tPLH tPHL Propagation Delay Time (D/U - RCO) tPLH tPHL Propagation Delay Time (D/U - MAX/ MIN) fMAX Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (LOAD) Minimum Set-up Time (SI, PI - CK) Minimum Set-up Time (S0, S1 - CK) Minimum Hold Time ns ns ns ns ns ns ns ns 6.2 31 37 MHz tW(H) tW(L) tW(L) ns ns ts ns ts ns th ns 6/13 M54HC191 Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 TA = 25C Min. Typ. 12 3 3 Max. 50 10 9 Value -40 to 85C Min. Max. 60 12 11 -55 to 125C Min. Max. 65 15 13 ns Unit tREM Minimum Removal Time (CLEAR) CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25C Min. Typ. 5 112 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50) 7/13 M54HC191 WAVEFORM 1: PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK)(f=1MHz; 50% duty cycle) WAVEFORM 2: PROPAGATION DELAY TIME, SETUP AND HOLD TIME (A-D TO LOAD) (f=1MHz; 50% duty cycle) 8/13 M54HC191 WAVEFORM 3: MINIMUM PULSE WIDTH (LOAD) AND REMOVAL TIME (LOAD TO CLOCK) (f=1MHz; 50% duty cycle) WAVEFORM 4: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 9/13 M54HC191 WAVEFORM 5: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 6: SETUP AND HOLD TIME (f=1MHz; 50% duty cycle) 10/13 M54HC191 DILC-16 MECHANICAL DATA mm. DIM. MIN. A a1 a2 B b b1 D e e1 e2 e3 F I K L 10.90 1.14 17.65 7.62 7.29 2.1 3.00 0.63 1.82 0.40 0.20 20.06 7.36 0.45 0.254 20.32 7.62 2.54 17.78 7.87 7.49 17.90 8.12 7.70 3.83 12.1 1.5 0.429 0.045 0.695 0.300 0.287 0.88 TYP MAX. 2.71 3.70 1.14 2.39 0.50 0.30 20.58 7.87 MIN. 0.083 0.118 0.025 0.072 0.016 0.008 0.790 0.290 0.018 0.010 0.800 0.300 0.100 0.700 0.310 0.295 0.705 0.320 0.303 0.151 0.476 0.059 0.035 TYP. MAX. 0.107 0.146 0.045 0.094 0.020 0.012 0.810 0.310 inch 0056437F 11/13 M54HC191 FPC-16 MECHANICAL DATA mm. DIM. MIN. A B C D E F G H L M N 0.38 6.0 18.75 0.33 0.38 4.31 22.0 0.43 6.75 9.76 1.49 0.102 8.76 0.127 8.89 1.27 0.43 0.48 0.015 0.237 0.738 0.013 0.015 0.170 0.867 0.017 TYP 6.91 9.94 MAX. 7.06 10.14 1.95 0.152 9.01 MIN. 0.266 0.384 0.059 0.004 0.345 0.005 0.350 0.050 0.017 0.019 TYP. 0.272 0.392 MAX. 0.278 0.399 0.077 0.006 0.355 inch F G D H 16 9 A N L 1 8 H E M C B 0016030E 12/13 M54HC191 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 13/13 |
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